The present invention relates to a semiconductor non-volatile memory device of the type which has a floating gate, to capture electric charge through a gate insulation film, and which utilizes, as a memory function, the change in the gate threshold voltage caused by the presence or absence of electric charge, or by the change of the polarity of the stored electric charge.
In general, semiconductor non-volatile memory devices can be roughly divided into those having an electrically conductive layer which accumulates an electric charge in the gate insulation film, (i.e., those of the floating gate type), and those which utilize the trap formed on the interface of dissimilar insulation films as a gate insulation film, such as those of the MNOS (metal nitride oxide semiconductor) type or those of the MAOS (metal alumina oxide semiconductor) type. According to these memory devices, the electric charge is accumulated in the floating gate or in the trap to utilize the gate threshold voltage as a memory function, which changes depending upon the presence or absence of the accumulated charge or depending upon the polarity of the electric charge.
In memory devices of the floating gate type, the electric charge is avalanche-injected, i.e., hot carriers produced by an avalanche breakdown are injected. In memory devices of the MNOS type, the electric charge is injected by utilizing the tunnel effect.
The conventional devices, however, have various defects. The most serious defect is that an extremely large voltage of reverse polarity is required during the so-called writing mode to inject the electric charge into the floating gate or into the trap, and accordingly, a special power source is required to write information.
The specification of Japanese Pat. No. 13142/80 discloses a memory device of the floating gate type which permits the avalanche breakdown to easily take place in the vicinity of the drain, to cope with the above-mentioned defect. Further, although the objects, functions and effects are different, the specification of U.S. Pat. No. 3,755,721 discloses a memory device of a similar construction.
With the conventional devices disclosed in the above-mentioned specifications, however, the same drain circuit operates when information is written or erased and when information is read. Therefore, even if the avalanche breakdown voltage is reduced during the writing mode, hot carriers are also generated in small amounts during the reading mode and are injected into the floating gate, whereby the gate threshold voltage is varied and unnecessary information is written. Accordingly, the writing and erasing voltages cannot be sufficiently reduced. If this reading problem can be solved, the avalanche breakdown voltage can be decreased to about 5 volts, by increasing the concentration in the P and N layers to a particular level. If the concentration is further increased, however, the tunnel effect occurs, which makes it difficult to decrease the avalanche breakdown voltage below 5 volts.
With the memory devices of the MNOS type which utilize the trap in the insulation film, the writing and erasing voltages can be decreased by reducing the thickness of the insulation film. When the thickness of the insulation film is reduced, however, the formation storage characteristics deteriorate, and carriers are injected during the reading mode. Therefore, the writing and erasing voltages cannot be sufficiently decreased.